A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

  1. Gonzalez-Toral, R.
  2. Reviriego, P.
  3. Maestro, J.A.
  4. Gao, Z.
Journal:
IEEE Transactions on Computers

ISSN: 1557-9956,  0018-9340

Year of publication: 2018

Volume: 67

Issue: 7

Pages: 1039-1045

Type: Article

DOI: 10.1109/TC.2018.2792445 GOOGLE SCHOLAR
Data source: Scopus