A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

  1. Gonzalez-Toral, R.
  2. Reviriego, P.
  3. Maestro, J.A.
  4. Gao, Z.
Aldizkaria:
IEEE Transactions on Computers

ISSN: 1557-9956,  0018-9340

Argitalpen urtea: 2018

Alea: 67

Zenbakia: 7

Orrialdeak: 1039-1045

Mota: Artikulua

DOI: 10.1109/TC.2018.2792445 GOOGLE SCHOLAR
Datuen iturria: Scopus