Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits

  1. Parra, P.
  2. Castro, J.
  3. Valencia, M.
  4. Acosta, A.J.
Proceedings:
Proceedings of SPIE - The International Society for Optical Engineering

ISSN: 0277-786X

Year of publication: 2005

Volume: 5837 PART II

Pages: 1003-1014

Type: Conference paper

DOI: 10.1117/12.608276 GOOGLE SCHOLAR
Data source: Scopus