ENRIQUE
SAN ANDRÉS SERRANO
Catedrático de universidad
Universidad Politécnica de Madrid
Madrid, EspañaPublicaciones en colaboración con investigadores/as de Universidad Politécnica de Madrid (4)
2017
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A robust method to determine the contact resistance using the van der Pauw set up
Measurement: Journal of the International Measurement Confederation, Vol. 98, pp. 151-158
2016
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Limitations of high pressure sputtering for amorphous silicon deposition
Materials Research Express, Vol. 3, Núm. 3
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Thermal Assessment of AlGaN/GaN MOS-HEMTs on Si Substrate Using Gd2O3 as Gate Dielectric
IEEE Transactions on Electron Devices, Vol. 63, Núm. 7, pp. 2729-2734
2005
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Interface quality of high-pressure reactive sputtered and atomic layer deposited titanium oxide thin films on silicon
2005 Spanish Conference on Electron Devices, Proceedings