![Foto de JOSÉ LUIS](/img/nophoto.png)
JOSÉ LUIS
IMAÑA PASCUAL
Profesor titular de universidad
Publicaciones (41) Publicaciones de JOSÉ LUIS IMAÑA PASCUAL
2024
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Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 71, Núm. 8, pp. 3915-3919
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Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia's Data Processing Unit Platform
IEEE Access, Vol. 12, pp. 38048-38056
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First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs)
2024 Optical Fiber Communications Conference and Exhibition, OFC 2024 - Proceedings
2023
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Decomposition of Dillon’s APN Permutation with Efficient Hardware Implementation
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks
Information Processing Letters, Vol. 182
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Hardware architecture of Dillon's APN permutation for different primitive polynomials
Microprocessors and Microsystems, Vol. 103
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INTERACTIVE RESOURCES TO ENHANCE SELF-LEARNING IN HIGHER EDUCATION
EDULEARN Proceedings
2022
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Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography
IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 69, Núm. 8, pp. 3297-3307
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Efficient Hardware Implementation of Finite Field Arithmetic AB+C + C for Binary Ring-LWE Based Post-Quantum Cryptography
IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 1222-1228
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Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography
Proceedings - 2022 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2022
2021
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LFSR-Based Bit-Serial Multipliers Using Irreducible Trinomials
IEEE Transactions on Computers, Vol. 70, Núm. 1, pp. 156-162
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Low-Delay FPGA-Based Implementation of Finite Field Multipliers
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, Núm. 8, pp. 2952-2956
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Optimized reversible quantum circuits for F28 multiplication
Quantum Information Processing, Vol. 20, Núm. 1
2020
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FPGA Implementation of Post-Quantum DME Cryptosystem
Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020
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High-throughput architecture for post-quantum DME cryptosystem
Integration, Vol. 75, pp. 114-121
2018
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Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials
Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018
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Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials
IEEE Transactions on Computers, Vol. 67, Núm. 6, pp. 898-904
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Reconfigurable implementation of GF(2m) bit-parallel multipliers
Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
2016
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Finite field arithmetic for RFID and sensor networks
Security in RFID and Sensor Networks (CRC Press), pp. 489-508
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High-Speed Polynomial Basis Multipliers over GF(2m) for Special Pentanomials
IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, Núm. 1, pp. 58-69