Publicacións (44) Publicacións de JOSÉ LUIS IMAÑA PASCUAL

2024

  1. Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 71, Núm. 8, pp. 3915-3919

  2. Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia's Data Processing Unit Platform

    IEEE Access, Vol. 12, pp. 38048-38056

  3. First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs)

    2024 Optical Fiber Communications Conference and Exhibition, OFC 2024 - Proceedings

  4. In-line rate encrypted links using pre-shared post-quantum keys and DPUs

    Scientific Reports, Vol. 14, Núm. 1

  5. The zero-tax data center: A use case through quantum resilient communications

    International Conference on Transparent Optical Networks

  6. Wireless and Fiber-Based Post-Quantum-Cryptography-Secured IPsec Tunnel

    Future Internet, Vol. 16, Núm. 8

2023

  1. Decomposition of Dillon’s APN Permutation with Efficient Hardware Implementation

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks

    Information Processing Letters, Vol. 182

  3. Hardware architecture of Dillon's APN permutation for different primitive polynomials

    Microprocessors and Microsystems, Vol. 103

  4. INTERACTIVE RESOURCES TO ENHANCE SELF-LEARNING IN HIGHER EDUCATION

    EDULEARN Proceedings

2022

  1. Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 69, Núm. 8, pp. 3297-3307

  2. Efficient Hardware Implementation of Finite Field Arithmetic AB+C + C for Binary Ring-LWE Based Post-Quantum Cryptography

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 1222-1228

  3. Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography

    Proceedings - 2022 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2022

2021

  1. LFSR-Based Bit-Serial Multipliers Using Irreducible Trinomials

    IEEE Transactions on Computers, Vol. 70, Núm. 1, pp. 156-162

  2. Low-Delay FPGA-Based Implementation of Finite Field Multipliers

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, Núm. 8, pp. 2952-2956

  3. Optimized reversible quantum circuits for F28 multiplication

    Quantum Information Processing, Vol. 20, Núm. 1

2020

  1. FPGA Implementation of Post-Quantum DME Cryptosystem

    Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020

  2. High-throughput architecture for post-quantum DME cryptosystem

    Integration, Vol. 75, pp. 114-121

2018

  1. Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials

    Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018

  2. Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials

    IEEE Transactions on Computers, Vol. 67, Núm. 6, pp. 898-904