LUIS
PIÑUEL MORENO
Profesor titular de universidad
JOSÉ FRANCISCO
TIRADO FERNÁNDEZ
Profesor emérito
JOSÉ FRANCISCO TIRADO FERNÁNDEZ-rekin lankidetzan egindako argitalpenak (40)
2017
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CEPRAM: Compression for Endurance in PCM RAM
Journal of Circuits, Systems and Computers, Vol. 26, Núm. 11
2015
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Non-negative Matrix Factorization on Low-Power Architectures and Accelerators: A Comparative Study
Computers and Electrical Engineering, Vol. 46, pp. 139-156
2014
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Write-aware replacement policies for PCM-based systems
Computer Journal, Vol. 58, Núm. 9, pp. 2000-2025
2013
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Increasing the Endurance of Phase-Change Memories with Cache Replacement Policies
Actas de las XXIV Jornadas de Paralelismo
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Reducing writes in phase-change memory environments by using efficient cache replacement policies
Proceedings -Design, Automation and Test in Europe, DATE
2012
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Reducing cache hierarchy energy consumption by predicting forwarding and disabling associative sets
Journal of Circuits, Systems and Computers, Vol. 21, Núm. 7
2011
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Hybrid timing-address oriented load-store queue filtering for an x86 architecture
IET Computers and Digital Techniques, Vol. 5, Núm. 2, pp. 145-157
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L1 data cache power reduction using a forwarding predictor
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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L1 data cache power reduction using a forwarding predictor
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2010
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Stack filter: Reducing L1 data cache power consumption
Journal of Systems Architecture, Vol. 56, Núm. 12, pp. 685-695
2009
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Replacing associative load queues: A timing-centric approach
IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511
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Stack oriented data cache filtering
Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009
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Using age registers for a simple load-store queue filtering
Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89
2008
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Energy reduction of the fetch mechanism through dynamic adaptation
IET Computers and Digital Techniques, Vol. 2, Núm. 2, pp. 94-107
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Memory disambiguation hardware: a Review
Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138
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Parallel implementation of the 2D discrete wavelet transform on graphics processing units: Filter Bank versus lifting
IEEE Transactions on Parallel and Distributed Systems, Vol. 19, Núm. 3, pp. 299-310
2006
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DMDC: Delayed Memory Dependence Checking through age-based filtering
Proceedings of the Annual International Symposium on Microarchitecture, MICRO
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LSQ: A power efficient and scalable implementation
IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398
2005
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A Per-Module adaptive fetch mechanism
Actas de las XVI Jornadas de Paralelismo. [JP'2005]
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A power-efficient and scalable load-store queue design
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)