Publicaciones en las que colabora con LUIS PIÑUEL MORENO (20)

2024

  1. Improving the Representativeness of Simulation Intervals for the Cache Memory System

    IEEE Access, Vol. 12, pp. 5973-5985

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2017

  1. CEPRAM: Compression for Endurance in PCM RAM

    Journal of Circuits, Systems and Computers, Vol. 26, Núm. 11

2014

  1. Write-aware replacement policies for PCM-based systems

    Computer Journal, Vol. 58, Núm. 9, pp. 2000-2025

2013

  1. Increasing the Endurance of Phase-Change Memories with Cache Replacement Policies

    Actas de las XXIV Jornadas de Paralelismo

  2. Reducing writes in phase-change memory environments by using efficient cache replacement policies

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Reducing cache hierarchy energy consumption by predicting forwarding and disabling associative sets

    Journal of Circuits, Systems and Computers, Vol. 21, Núm. 7

2011

  1. L1 data cache power reduction using a forwarding predictor

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. L1 data cache power reduction using a forwarding predictor

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2010

  1. Stack filter: Reducing L1 data cache power consumption

    Journal of Systems Architecture, Vol. 56, Núm. 12, pp. 685-695

2009

  1. Replacing associative load queues: A timing-centric approach

    IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511

  2. Stack oriented data cache filtering

    Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009

  3. Using age registers for a simple load-store queue filtering

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89

2008

  1. Memory disambiguation hardware: a Review

    Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138

2006

  1. DMDC: Delayed Memory Dependence Checking through age-based filtering

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. LSQ: A power efficient and scalable implementation

    IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398

  3. Substituting associative load queue with simple hash tables in out-of-order microprocessors

    Proceedings of the International Symposium on Low Power Electronics and Design

2005

  1. A power-efficient and scalable load-store queue design

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Gestión eficiente de la LSQ basada en mecanismos de filtrado

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

  3. Load-store queue management: An energy-efficient design based on a state-filtering mechanism

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors