Publikationen, an denen er mitarbeitet DANIEL ÁNGEL CHAVER MARTÍNEZ (24)

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2017

  1. Towards completely fair scheduling on asymmetric single-ISA multicore processors

    Journal of Parallel and Distributed Computing, Vol. 102, pp. 115-131

2016

  1. OpenIRS-UCM: An Integral Solution for Interactive Response Systems

    International Journal of Engineering Education, Vol. 32, Núm. 2, pp. 873-885

2015

  1. ACFS: A completely fair scheduler for asymmetric single-ISA multicore systems

    Proceedings of the ACM Symposium on Applied Computing

  2. An OS-Oriented performance monitoring tool for multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2014

  1. Exploring the throughput-fairness trade-off on asymmetric multicore systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Improving peLIFO cache replacement policy: Hardware reduction and thread-aware extension

    Journal of Circuits, Systems and Computers, Vol. 23, Núm. 4

  3. Write-aware replacement policies for PCM-based systems

    Computer Journal, Vol. 58, Núm. 9, pp. 2000-2025

2013

  1. Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling

    Performance Evaluation Review

  2. Increasing the Endurance of Phase-Change Memories with Cache Replacement Policies

    Actas de las XXIV Jornadas de Paralelismo

  3. Reducing writes in phase-change memory environments by using efficient cache replacement policies

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. OpenIRS-UCM: An open-source multi-platform for interactive response systems

    Annual Conference on Innovation and Technology in Computer Science Education, ITiCSE

  2. Reducing cache hierarchy energy consumption by predicting forwarding and disabling associative sets

    Journal of Circuits, Systems and Computers, Vol. 21, Núm. 7

2011

  1. L1 data cache power reduction using a forwarding predictor

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. L1 data cache power reduction using a forwarding predictor

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2009

  1. Replacing associative load queues: A timing-centric approach

    IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511

  2. Using age registers for a simple load-store queue filtering

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89

2008

  1. Memory disambiguation hardware: a Review

    Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138

2006

  1. DMDC: Delayed Memory Dependence Checking through age-based filtering

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. LSQ: A power efficient and scalable implementation

    IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398