Publicaciones (48) Publicaciones de JOSÉ IGNACIO GÓMEZ PÉREZ

2024

  1. Improving the Representativeness of Simulation Intervals for the Cache Memory System

    IEEE Access, Vol. 12, pp. 5973-5985

2023

  1. COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

    Journal of Systems Architecture, Vol. 145

2022

  1. Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

    ACM Transactions on Embedded Computing Systems, Vol. 21, Núm. 1

  2. Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, Núm. 12, pp. 5327-5332

2021

  1. RVFPGA: Using a RISC-V core targeted to an FPGA in computer architecture education

    Proceedings - 2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021

2020

  1. Spatio-Temporal Resolution of Irradiance Samples in Machine Learning Approaches for Irradiance Forecasting

    IEEE Access, Vol. 8, pp. 51518-51531

2019

  1. A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs

    Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

2018

  1. A CPU-GPU Parallel Ant Colony Optimization Solver for the Vehicle Routing Problem

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

    Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

  3. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

    PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)

2017

  1. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems

    2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

2016

  1. OpenIRS-UCM: An Integral Solution for Interactive Response Systems

    International Journal of Engineering Education, Vol. 32, Núm. 2, pp. 873-885

2015

  1. A power measurement environment for PCIe accelerators: Application to the Intel Xeon Phi

    Computer Science - Research and Development, Vol. 30, Núm. 2, pp. 115-124

  2. System level exploration of a STT-MRAM based Level 1 Data-Cache

    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)

  3. System level exploration of a STT-MRAM based level 1 data-cache

    Proceedings -Design, Automation and Test in Europe, DATE

2014

  1. Adaptive mapping and parameter selection scheme to improve automatic code generation for GPUs

    Proceedings of the 12th ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2014

  2. Feasibility Exploration of NVM based I-Cache through MSHR Enhancements

    2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE)

  3. Feasibility exploration of NVM based I-cache through MSHR enhancements

    Proceedings -Design, Automation and Test in Europe, DATE

  4. Online evaluation methodology of laboratory sessions in computer science degrees

    Revista Iberoamericana de Tecnologias del Aprendizaje, Vol. 9, Núm. 4, pp. 122-130