Publicaciones en las que colabora con LUIS PIÑUEL MORENO (29)

2023

  1. RVfpga: Computer Architecture Course and MOOC Using a RISC-V SoC Targeted to an FPGA and Simulation

    ASEE Annual Conference and Exposition, Conference Proceedings

2021

  1. RVFPGA: Using a RISC-V core targeted to an FPGA in computer architecture education

    Proceedings - 2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2014

  1. Write-aware replacement policies for PCM-based systems

    Computer Journal, Vol. 58, Núm. 9, pp. 2000-2025

2013

  1. Increasing the Endurance of Phase-Change Memories with Cache Replacement Policies

    Actas de las XXIV Jornadas de Paralelismo

  2. Reducing writes in phase-change memory environments by using efficient cache replacement policies

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Reducing cache hierarchy energy consumption by predicting forwarding and disabling associative sets

    Journal of Circuits, Systems and Computers, Vol. 21, Núm. 7

2011

  1. Hybrid timing-address oriented load-store queue filtering for an x86 architecture

    IET Computers and Digital Techniques, Vol. 5, Núm. 2, pp. 145-157

  2. L1 data cache power reduction using a forwarding predictor

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. L1 data cache power reduction using a forwarding predictor

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2009

  1. Replacing associative load queues: A timing-centric approach

    IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511

  2. Using age registers for a simple load-store queue filtering

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89

2008

  1. Energy reduction of the fetch mechanism through dynamic adaptation

    IET Computers and Digital Techniques, Vol. 2, Núm. 2, pp. 94-107

  2. Memory disambiguation hardware: a Review

    Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138

2006

  1. DMDC: Delayed Memory Dependence Checking through age-based filtering

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. LSQ: A power efficient and scalable implementation

    IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398

  3. Substituting associative load queue with simple hash tables in out-of-order microprocessors

    Proceedings of the International Symposium on Low Power Electronics and Design

2005

  1. A Per-Module adaptive fetch mechanism

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

  2. A power-efficient and scalable load-store queue design

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Energy-aware fetch mechanism: Trace cache and BTB customization

    Proceedings of the International Symposium on Low Power Electronics and Design