Publicaciones en las que colabora con Alfonso Sánchez-Macián (45)

2022

  1. An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique

    Microprocessors and Microsystems, Vol. 90

  2. Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 635-647

  3. Towards an error-free 3-D memory for space applications

    Advances in Space Research, Vol. 70, Núm. 7, pp. 1917-1924

2021

  1. Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories

    IEEE Transactions on Emerging Topics in Computing, Vol. 9, Núm. 4, pp. 2139-2145

  2. Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, Núm. 4, pp. 1438-1442

  3. Fault injection emulation for systems in FPGAs: Tools, techniques and methodology, a tutorial

    Sensors (Switzerland), Vol. 21, Núm. 4, pp. 1-23

  4. Low delay non-binary error correction codes based on Orthogonal Latin Squares

    Integration, Vol. 76, pp. 55-60

  5. Reduced length redundancy adaptive protection for the cascaded integrator-comb interpolation filter on FPGA

    Microelectronics Reliability, Vol. 118

2020

  1. A methodology to analyze the fault tolerance of demosaicking methods against memory single event functional interrupts (Sefis)

    Electronics (Switzerland), Vol. 9, Núm. 10, pp. 1-12

  2. An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Núm. 5, pp. 1336-1340

  3. Analysis of the critical bits of a RISC-V processor implemented in an SRAM-based FPGA for space applications

    Electronics (Switzerland), Vol. 9, Núm. 1

  4. Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation

    ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

  5. Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction

    IEEE Transactions on Device and Materials Reliability, Vol. 20, Núm. 2, pp. 390-394

  6. Extended symbol correction algorithm for group testing based non-binary error correction codes of minimum distance dq < 5

    Microelectronics Reliability, Vol. 113

  7. Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, Núm. 12, pp. 3362-3366

  8. Radiation Hardened Digital Direct Synthesizer with CORDIC for Spaceborne Applications

    IEEE Access, Vol. 8, pp. 83167-83176

  9. Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes

    2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020

  10. Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA

    Circuits, Systems, and Signal Processing, Vol. 39, Núm. 11, pp. 5529-5542

2019

  1. ACME: A tool to improve configuration memory fault injection in SRAM-based FPGAS

    IEEE Access, Vol. 7, pp. 128153-128161

  2. Enhanced Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories

    IEEE Transactions on Nanotechnology, Vol. 18, pp. 1023-1026