Publicacions en què col·labora amb Luis Aranda Barjola (18)

2022

  1. ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, Núm. 3, pp. 1577-1581

2021

  1. Fault injection emulation for systems in FPGAs: Tools, techniques and methodology, a tutorial

    Sensors (Switzerland), Vol. 21, Núm. 4, pp. 1-23

  2. Reliability Analysis of ASIC Designs with Xilinx SRAM-Based FPGAs

    IEEE Access, Vol. 9, pp. 140676-140685

2020

  1. A methodology to analyze the fault tolerance of demosaicking methods against memory single event functional interrupts (Sefis)

    Electronics (Switzerland), Vol. 9, Núm. 10, pp. 1-12

  2. An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Núm. 5, pp. 1336-1340

  3. Analysis of the critical bits of a RISC-V processor implemented in an SRAM-based FPGA for space applications

    Electronics (Switzerland), Vol. 9, Núm. 1

  4. Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction

    IEEE Transactions on Device and Materials Reliability, Vol. 20, Núm. 2, pp. 390-394

  5. Radiation Hardened Digital Direct Synthesizer with CORDIC for Spaceborne Applications

    IEEE Access, Vol. 8, pp. 83167-83176

  6. Reliability analysis of the shyloc ccsds123 ip core for lossless hyperspectral image compression using cots FPGAs

    Electronics (Switzerland), Vol. 9, Núm. 10, pp. 1-15

  7. Toward a fault-tolerant star tracker for small satellite applications

    IEEE Transactions on Aerospace and Electronic Systems, Vol. 56, Núm. 5, pp. 3421-3431

2019

  1. ACME: A tool to improve configuration memory fault injection in SRAM-based FPGAS

    IEEE Access, Vol. 7, pp. 128153-128161

  2. Enhancing instruction TLB resilience to soft errors

    IEEE Transactions on Computers, Vol. 68, Núm. 2, pp. 214-224

  3. Protection scheme for star tracker images

    IEEE Transactions on Aerospace and Electronic Systems, Vol. 55, Núm. 1, pp. 486-492

  4. Reducing false positives due to double adjacent errors in instruction TLBs

    Microelectronics Reliability, Vol. 102

2018

  1. A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, Núm. 3, pp. 376-380

  2. Protecting image processing pipelines against configuration memory errors in sram-based fpgas

    Electronics (Switzerland), Vol. 7, Núm. 11

2017

  1. Error Detection Technique for a Median Filter

    IEEE Transactions on Nuclear Science, Vol. 64, Núm. 8, pp. 2219-2226

2016

  1. A fault-tolerant implementation of the median filter

    Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS