FRANCISCO MIGUEL
GARCÍA HERRERO
Profesor titular de universidad
JUAN ANTONIO
MAESTRO DE LA CUERDA
Catedrático de universidad
Publicaciones en las que colabora con JUAN ANTONIO MAESTRO DE LA CUERDA (20)
2023
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Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension
IEEE Transactions on Aerospace and Electronic Systems, Vol. 59, Núm. 5, pp. 5835-5846
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RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography
IEEE Transactions on Computers, Vol. 72, Núm. 3, pp. 682-692
2022
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A new radiation-hardened architecture for holographic memory address calculation
Alexandria Engineering Journal, Vol. 61, Núm. 8, pp. 6181-6190
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ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, Núm. 3, pp. 1577-1581
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Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors
Computers and Electrical Engineering, Vol. 99
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Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale
IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 635-647
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Towards an error-free 3-D memory for space applications
Advances in Space Research, Vol. 70, Núm. 7, pp. 1917-1924
2021
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Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories
IEEE Transactions on Emerging Topics in Computing, Vol. 9, Núm. 4, pp. 2139-2145
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Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, Núm. 4, pp. 1438-1442
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Fault injection emulation for systems in FPGAs: Tools, techniques and methodology, a tutorial
Sensors (Switzerland), Vol. 21, Núm. 4, pp. 1-23
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Low delay non-binary error correction codes based on Orthogonal Latin Squares
Integration, Vol. 76, pp. 55-60
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Reliability Analysis of ASIC Designs with Xilinx SRAM-Based FPGAs
IEEE Access, Vol. 9, pp. 140676-140685
2020
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Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction
IEEE Transactions on Device and Materials Reliability, Vol. 20, Núm. 2, pp. 390-394
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Extended symbol correction algorithm for group testing based non-binary error correction codes of minimum distance dq < 5
Microelectronics Reliability, Vol. 113
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Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, Núm. 12, pp. 3362-3366
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Radiation Hardened Digital Direct Synthesizer with CORDIC for Spaceborne Applications
IEEE Access, Vol. 8, pp. 83167-83176
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Reliability analysis of the shyloc ccsds123 ip core for lossless hyperspectral image compression using cots FPGAs
Electronics (Switzerland), Vol. 9, Núm. 10, pp. 1-15
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Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA
Circuits, Systems, and Signal Processing, Vol. 39, Núm. 11, pp. 5529-5542
2019
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Enhanced Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories
IEEE Transactions on Nanotechnology, Vol. 18, pp. 1023-1026
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Reliability of 3D memories using Orthogonal Latin Square codes
Microelectronics Reliability, Vol. 95, pp. 74-80