Publicaciones en colaboración con investigadores/as de KU Leuven (46)

2024

  1. Improving the Representativeness of Simulation Intervals for the Cache Memory System

    IEEE Access, Vol. 12, pp. 5973-5985

2023

  1. COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

    Journal of Systems Architecture, Vol. 145

  2. Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks

    Information Processing Letters, Vol. 182

2022

  1. Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, Núm. 12, pp. 5327-5332

2021

  1. Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

    IEEE Transactions on Device and Materials Reliability, Vol. 21, Núm. 2, pp. 258-266

2019

  1. A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs

    Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

2018

  1. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

    Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

  2. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

    PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)

2017

  1. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems

    2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

2015

  1. System level exploration of a STT-MRAM based Level 1 Data-Cache

    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)

  2. System level exploration of a STT-MRAM based level 1 data-cache

    Proceedings -Design, Automation and Test in Europe, DATE

2014

  1. Configuration mapping algorithms to reduce energy and time reconfiguration overheads in reconfigurable systems

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 6, pp. 1248-1261

2010

  1. Software metadata: Systematic characterization of the memory behaviour of dynamic applications

    Journal of Systems and Software, Vol. 83, Núm. 6, pp. 1051-1075

2009

  1. Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems

    Journal of Systems and Software, Vol. 82, Núm. 4, pp. 590-602

2008

  1. Efficiently scheduling runtime reconfigurations

    ACM Transactions on Design Automation of Electronic Systems, Vol. 13, Núm. 4

  2. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded Software Metadata Information

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

  3. Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures

    Integration, the VLSI Journal, Vol. 41, Núm. 1, pp. 38-48

2007

  1. Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Energy-aware compilation and hardware design for VLIW embedded systems

    International Journal of Embedded Systems, Vol. 3, Núm. 1-2, pp. 73-82