Publicaciones en las que colabora con LUIS PIÑUEL MORENO (33)

2023

  1. PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core

    Proceedings of the 20th ACM International Conference on Computing Frontiers 2023, CF 2023

2022

  1. Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions

    2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

  2. PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 3, pp. 1241-1252

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2015

  1. A power measurement environment for PCIe accelerators: Application to the Intel Xeon Phi

    Computer Science - Research and Development, Vol. 30, Núm. 2, pp. 115-124

  2. Non-negative Matrix Factorization on Low-Power Architectures and Accelerators: A Comparative Study

    Computers and Electrical Engineering, Vol. 46, pp. 139-156

2013

  1. Funcionamiento de la herramienta OpenIRS-UCM y sus sinergias con Moodle

    Valorar, validar y difundir Campus Virtual

2011

  1. Hybrid timing-address oriented load-store queue filtering for an x86 architecture

    IET Computers and Digital Techniques, Vol. 5, Núm. 2, pp. 145-157

2009

  1. Replacing associative load queues: A timing-centric approach

    IEEE Transactions on Computers, Vol. 58, Núm. 4, pp. 496-511

  2. TeleTest, un nuevo sistema de respuesta interactiva

    Buenas prácticas e indicios de calidad

  3. Using age registers for a simple load-store queue filtering

    Journal of Systems Architecture, Vol. 55, Núm. 2, pp. 79-89

2008

  1. Energy reduction of the fetch mechanism through dynamic adaptation

    IET Computers and Digital Techniques, Vol. 2, Núm. 2, pp. 94-107

  2. Memory disambiguation hardware: a Review

    Journal of Computer Science and Technology, Vol. 8, Núm. 3, pp. 132-138

  3. Parallel implementation of the 2D discrete wavelet transform on graphics processing units: Filter Bank versus lifting

    IEEE Transactions on Parallel and Distributed Systems, Vol. 19, Núm. 3, pp. 299-310

2006

  1. DMDC: Delayed Memory Dependence Checking through age-based filtering

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. LSQ: A power efficient and scalable implementation

    IEE Proceedings: Computers and Digital Techniques, Vol. 153, Núm. 6, pp. 389-398

  3. Substituting associative load queue with simple hash tables in out-of-order microprocessors

    Proceedings of the International Symposium on Low Power Electronics and Design

2005

  1. A Per-Module adaptive fetch mechanism

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

  2. A power-efficient and scalable load-store queue design

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Energy-aware fetch mechanism: Trace cache and BTB customization

    Proceedings of the International Symposium on Low Power Electronics and Design