Instituto de Tecnología del Conocimiento (ITC)
Centro/Instituto
Interuniversity Microelectronics Centre
Lovaina, BélgicaPublicaciones en colaboración con investigadores/as de Interuniversity Microelectronics Centre (14)
2013
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System-level memory management based on statistical variability compensation for frame-based applications
Transactions on Embedded Computing Systems
2010
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Statistical approach in a system level methodology to deal with process variation
Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010
2009
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System-level process variability compensation on memory organizations. on the scalability of multi-mode memories
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2008
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Combining system scenarios and configurable memories to tolerate unpredictability
ACM Transactions on Design Automation of Electronic Systems, Vol. 13, Núm. 3
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Efficiently scheduling runtime reconfigurations
ACM Transactions on Design Automation of Electronic Systems, Vol. 13, Núm. 4
2007
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Memory hierarchy for high-performance and energy-aware reconfigurable systems
IET Computers and Digital Techniques, Vol. 1, Núm. 5, pp. 565-571
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Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation
ACM International Conference Proceeding Series
2006
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A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
20th International Parallel and Distributed Processing Symposium, IPDPS 2006
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System-level process variability compensation on memory organizations of dynamic applications: A case study
Proceedings - International Symposium on Quality Electronic Design, ISQED
2005
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Improving superword level parallelism support in modern compilers
CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis
2004
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A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs
Microprocessors and Microsystems, Vol. 28, Núm. 5-6 SPEC. ISS., pp. 291-301
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Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware
Proceedings - Design Automation Conference
2003
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Application of task concurrency management on dynamically reconfigurable hardware platforms
IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
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Run-time minimization of reconfiguration overhead in dynamically reconfigurable systems
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2778, pp. 585-594