Publicacións en colaboración con investigadores/as de Interuniversity Microelectronics Centre (66)

2024

  1. Improving the Representativeness of Simulation Intervals for the Cache Memory System

    IEEE Access, Vol. 12, pp. 5973-5985

2023

  1. COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

    Journal of Systems Architecture, Vol. 145

2022

  1. Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

    ACM Transactions on Embedded Computing Systems, Vol. 21, Núm. 1

  2. Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, Núm. 12, pp. 5327-5332

2021

  1. Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

    IEEE Transactions on Device and Materials Reliability, Vol. 21, Núm. 2, pp. 258-266

2020

  1. Analysis of functional errors produced by long-Term workload-dependent bti degradation in ultralow power processors

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Núm. 10, pp. 2122-2133

2019

  1. A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs

    Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

2018

  1. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

    Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

2017

  1. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems

    Proceedings - IEEE International Symposium on Circuits and Systems

2015

  1. Placement of linked dynamic data structures over heterogeneous memories in embedded systems

    ACM Transactions on Embedded Computing Systems, Vol. 14, Núm. 2, pp. 37

  2. System level exploration of a STT-MRAM based level 1 data-cache

    Proceedings -Design, Automation and Test in Europe, DATE

2014

  1. Feasibility exploration of NVM based I-cache through MSHR enhancements

    Proceedings -Design, Automation and Test in Europe, DATE

2013

  1. Design exploration of a NVM based hybrid instruction memory organization for embedded platforms

    Design Automation for Embedded Systems, Vol. 7, Núm. 5, pp. 459-483

  2. Design space exploration of distributed loop buffer architectures with incompatible loop-nest organisations in embedded systems

    Journal of Signal Processing Systems, Vol. 72, Núm. 1, pp. 69-85

  3. Energy impact in the design space exploration of loop buffer schemes in embedded systems

    IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

  4. Polyhedral parallel code generation for CUDA

    Transactions on Architecture and Code Optimization, Vol. 9, Núm. 4

  5. Survey of low-energy techniques for instruction memory organisations in embedded systems

    Journal of Signal Processing Systems, Vol. 70, Núm. 1, pp. 1-19

  6. System-level memory management based on statistical variability compensation for frame-based applications

    Transactions on Embedded Computing Systems

2012

  1. IMOSIM: Exploration tool for instruction memory organisations based on accurate cycle-level energy modelling

    2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

  2. Power impact of loop buffer schemes for biomedical Wireless Sensor Nodes

    Sensors (Switzerland), Vol. 12, Núm. 11, pp. 15088-15118