A pseudo relay-insensitive timing model to synthesising low-power asynchronous circuits

  1. Garnica, O.
  2. Lanchares, J.
  3. Hermida, R.
Aktak:
Proceedings -Design, Automation and Test in Europe, DATE

ISSN: 1530-1591

Argitalpen urtea: 2001

Orrialdeak: 810

Mota: Biltzar ekarpena

DOI: 10.1109/DATE.2001.915146 GOOGLE SCHOLAR
Datuen iturria: Scopus