A pseudo relay-insensitive timing model to synthesising low-power asynchronous circuits

  1. Garnica, O.
  2. Lanchares, J.
  3. Hermida, R.
Actas:
Proceedings -Design, Automation and Test in Europe, DATE

ISSN: 1530-1591

Ano de publicación: 2001

Páxinas: 810

Tipo: Achega congreso

DOI: 10.1109/DATE.2001.915146 GOOGLE SCHOLAR
Fonte de datos: Scopus