Publicaciones en las que colabora con Pedro Reviriego Vasallo (171)

2020

  1. Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes

    2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020

  2. Toward a fault-tolerant star tracker for small satellite applications

    IEEE Transactions on Aerospace and Electronic Systems, Vol. 56, Núm. 5, pp. 3421-3431

2019

  1. An Alu protection methodology for soft processors on SRAM-based FPGAs

    IEEE Transactions on Computers, Vol. 68, Núm. 9, pp. 1404-1410

  2. Enhancing instruction TLB resilience to soft errors

    IEEE Transactions on Computers, Vol. 68, Núm. 2, pp. 214-224

  3. Protection scheme for star tracker images

    IEEE Transactions on Aerospace and Electronic Systems, Vol. 55, Núm. 1, pp. 486-492

  4. Reducing false positives due to double adjacent errors in instruction TLBs

    Microelectronics Reliability, Vol. 102

2018

  1. A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, Núm. 3, pp. 376-380

  2. A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

    IEEE Transactions on Computers, Vol. 67, Núm. 7, pp. 1039-1045

  3. A fast technique to reduce power consumption on linear block codes used to protect registers

    IEEE Transactions on Device and Materials Reliability, Vol. 18, Núm. 2, pp. 189-196

  4. An Efficient Methodology for On-Chip SEU Injection in Flip-Flops for Xilinx FPGAs

    IEEE Transactions on Nuclear Science, Vol. 65, Núm. 4, pp. 989-996

  5. An efficient fault-tolerance design for integer parallel matrix-vector multiplications

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, Núm. 1, pp. 211-215

  6. Efficient Fault-Tolerant Design for Parallel Matched Filters

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, Núm. 3, pp. 366-370

  7. Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs

    IEEE Transactions on Computers, Vol. 67, Núm. 2, pp. 299-304

  8. Evaluating the Impact of the Instruction Set on Microprocessor Reliability to Soft Errors

    IEEE Transactions on Device and Materials Reliability, Vol. 18, Núm. 1, pp. 70-79

  9. Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

    Microelectronics Reliability

  10. Majority Voting-Based Reduced Precision Redundancy Adders

    IEEE Transactions on Device and Materials Reliability, Vol. 18, Núm. 1, pp. 122-124

  11. Modular fault tolerant processor architecture on a SoC for space

    Microelectronics Reliability, Vol. 83, pp. 84-90

  12. Multiple Cell Upset Injection in BRAMs for Xilinx FPGAS

    IEEE Transactions on Device and Materials Reliability, Vol. 18, Núm. 4, pp. 636-638

  13. Protecting image processing pipelines against configuration memory errors in sram-based fpgas

    Electronics (Switzerland), Vol. 7, Núm. 11

  14. Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, Núm. 4, pp. 1293-1302