Publicaciones en colaboración con investigadores/as de Harbin Institute of Technology (12)

2020

  1. Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes

    2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020

2018

  1. Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

    Microelectronics Reliability

  2. Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, Núm. 4, pp. 1293-1302

2017

  1. A method to recover critical bits under a double error in SEC-DED protected memories

    Microelectronics Reliability

  2. A scheme to reduce the number of parity check bits in orthogonal Latin square codes

    IEEE Transactions on Reliability, Vol. 66, Núm. 2, pp. 518-528

  3. Comments on “Extend orthogonal Latin square codes for 32-bit data protection in memory applications” Microelectron. Reliab. 63, 278–283 (2016)

    Microelectronics Reliability

  4. Single event transient tolerant bloom filter implementations

    IEEE Transactions on Computers, Vol. 66, Núm. 10, pp. 1831-1836

2016

  1. An efficient single and double-adjacent error correcting parallel decoder for the (24,12) extended Golay code

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, Núm. 4, pp. 1603-1606

  2. Efficient implementation of single event upset tolerant register comparison

    Electronics Letters, Vol. 52, Núm. 23, pp. 1922-1923

  3. Odd-weight-column SEC-DED-TAED codes

    Electronics Letters, Vol. 52, Núm. 2, pp. 119-120

  4. Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes

    IEEE Transactions on Device and Materials Reliability, Vol. 16, Núm. 2, pp. 269-271

  5. Unequal error protection codes derived from SEC-DED codes

    Electronics Letters, Vol. 52, Núm. 8, pp. 619-620