Publicaciones en colaboración con investigadores/as de Universidad Nebrija (209)

2022

  1. A new radiation-hardened architecture for holographic memory address calculation

    Alexandria Engineering Journal, Vol. 61, Núm. 8, pp. 6181-6190

  2. ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, Núm. 3, pp. 1577-1581

  3. An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique

    Microprocessors and Microsystems, Vol. 90

  4. Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors

    Computers and Electrical Engineering, Vol. 99

  5. Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 635-647

  6. Towards an error-free 3-D memory for space applications

    Advances in Space Research, Vol. 70, Núm. 7, pp. 1917-1924

2020

  1. A methodology to analyze the fault tolerance of demosaicking methods against memory single event functional interrupts (Sefis)

    Electronics (Switzerland), Vol. 9, Núm. 10, pp. 1-12

  2. An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Núm. 5, pp. 1336-1340

  3. Analysis of the critical bits of a RISC-V processor implemented in an SRAM-based FPGA for space applications

    Electronics (Switzerland), Vol. 9, Núm. 1

  4. Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation

    ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

  5. Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction

    IEEE Transactions on Device and Materials Reliability, Vol. 20, Núm. 2, pp. 390-394

  6. Extended symbol correction algorithm for group testing based non-binary error correction codes of minimum distance dq < 5

    Microelectronics Reliability, Vol. 113

  7. Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, Núm. 12, pp. 3362-3366