Publicaciones (215) Publicaciones de JUAN ANTONIO MAESTRO DE LA CUERDA

2023

  1. Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension

    IEEE Transactions on Aerospace and Electronic Systems, Vol. 59, Núm. 5, pp. 5835-5846

  2. RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography

    IEEE Transactions on Computers, Vol. 72, Núm. 3, pp. 682-692

2022

  1. A new radiation-hardened architecture for holographic memory address calculation

    Alexandria Engineering Journal, Vol. 61, Núm. 8, pp. 6181-6190

  2. ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, Núm. 3, pp. 1577-1581

  3. An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique

    Microprocessors and Microsystems, Vol. 90

  4. Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors

    Computers and Electrical Engineering, Vol. 99

  5. Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 635-647

  6. Towards an error-free 3-D memory for space applications

    Advances in Space Research, Vol. 70, Núm. 7, pp. 1917-1924

2021

  1. Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories

    IEEE Transactions on Emerging Topics in Computing, Vol. 9, Núm. 4, pp. 2139-2145

  2. Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, Núm. 4, pp. 1438-1442

  3. Fault injection emulation for systems in FPGAs: Tools, techniques and methodology, a tutorial

    Sensors (Switzerland), Vol. 21, Núm. 4, pp. 1-23

  4. Low delay non-binary error correction codes based on Orthogonal Latin Squares

    Integration, Vol. 76, pp. 55-60

  5. Reduced length redundancy adaptive protection for the cascaded integrator-comb interpolation filter on FPGA

    Microelectronics Reliability, Vol. 118

  6. Reliability Analysis of ASIC Designs with Xilinx SRAM-Based FPGAs

    IEEE Access, Vol. 9, pp. 140676-140685

2020

  1. A methodology to analyze the fault tolerance of demosaicking methods against memory single event functional interrupts (Sefis)

    Electronics (Switzerland), Vol. 9, Núm. 10, pp. 1-12

  2. An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Núm. 5, pp. 1336-1340

  3. Analysis of the critical bits of a RISC-V processor implemented in an SRAM-based FPGA for space applications

    Electronics (Switzerland), Vol. 9, Núm. 1

  4. Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation

    ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

  5. Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction

    IEEE Transactions on Device and Materials Reliability, Vol. 20, Núm. 2, pp. 390-394

  6. Extended symbol correction algorithm for group testing based non-binary error correction codes of minimum distance dq < 5

    Microelectronics Reliability, Vol. 113