Publicaciones en colaboración con investigadores/as de Universidad Nebrija (25)

2023

  1. RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography

    IEEE Transactions on Computers, Vol. 72, Núm. 3, pp. 682-692

2022

  1. A new radiation-hardened architecture for holographic memory address calculation

    Alexandria Engineering Journal, Vol. 61, Núm. 8, pp. 6181-6190

  2. ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, Núm. 3, pp. 1577-1581

  3. Design and implementation of efficient QCA full-adders using fault-tolerant majority gates

    Journal of Supercomputing, Vol. 78, Núm. 6, pp. 8056-8080

  4. Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors

    Computers and Electrical Engineering, Vol. 99

  5. Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 635-647

  6. Towards an error-free 3-D memory for space applications

    Advances in Space Research, Vol. 70, Núm. 7, pp. 1917-1924

2021

  1. Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories

    IEEE Transactions on Emerging Topics in Computing, Vol. 9, Núm. 4, pp. 2139-2145

  2. Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, Núm. 4, pp. 1438-1442

  3. Fault injection emulation for systems in FPGAs: Tools, techniques and methodology, a tutorial

    Sensors (Switzerland), Vol. 21, Núm. 4, pp. 1-23

  4. Low delay non-binary error correction codes based on Orthogonal Latin Squares

    Integration, Vol. 76, pp. 55-60

  5. Reliability Analysis of ASIC Designs with Xilinx SRAM-Based FPGAs

    IEEE Access, Vol. 9, pp. 140676-140685

  6. Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes

    IEEE Access, Vol. 9, pp. 138734-138743

2020

  1. Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction

    IEEE Transactions on Device and Materials Reliability, Vol. 20, Núm. 2, pp. 390-394

  2. Extended symbol correction algorithm for group testing based non-binary error correction codes of minimum distance dq < 5

    Microelectronics Reliability, Vol. 113

  3. Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, Núm. 12, pp. 3362-3366

  4. Radiation Hardened Digital Direct Synthesizer with CORDIC for Spaceborne Applications

    IEEE Access, Vol. 8, pp. 83167-83176

  5. Reliability analysis of the shyloc ccsds123 ip core for lossless hyperspectral image compression using cots FPGAs

    Electronics (Switzerland), Vol. 9, Núm. 10, pp. 1-15

  6. Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA

    Circuits, Systems, and Signal Processing, Vol. 39, Núm. 11, pp. 5529-5542

2019

  1. A test vector generation method based on symbol error probabilities for low-complexity chase soft-decision reed-solomon decoding

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, Núm. 6, pp. 2198-2207