FRANCISCO MIGUEL
GARCÍA HERRERO
Profesor titular de universidad
Publications (53) Publications de FRANCISCO MIGUEL GARCÍA HERRERO
2024
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Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes
Quantum, Vol. 8
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Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration
IEEE Transactions on Circuits and Systems II: Express Briefs
2023
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Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension
IEEE Transactions on Aerospace and Electronic Systems, Vol. 59, Núm. 5, pp. 5835-5846
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Layered Decoding of Quantum LDPC Codes
2023 12th International Symposium on Topics in Coding, ISTC 2023
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RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography
IEEE Transactions on Computers, Vol. 72, Núm. 3, pp. 682-692
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Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures
EPJ Quantum Technology, Vol. 10, Núm. 1
2022
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A new radiation-hardened architecture for holographic memory address calculation
Alexandria Engineering Journal, Vol. 61, Núm. 8, pp. 6181-6190
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ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, Núm. 3, pp. 1577-1581
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Design and implementation of efficient QCA full-adders using fault-tolerant majority gates
Journal of Supercomputing, Vol. 78, Núm. 6, pp. 8056-8080
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Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors
Computers and Electrical Engineering, Vol. 99
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Project-Based Learning with historic buildings: immersion in real training environments for the Degree in Technical Architecture
CEUR Workshop Proceedings
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Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale
IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 2, pp. 635-647
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Towards an error-free 3-D memory for space applications
Advances in Space Research, Vol. 70, Núm. 7, pp. 1917-1924
2021
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Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories
IEEE Transactions on Emerging Topics in Computing, Vol. 9, Núm. 4, pp. 2139-2145
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Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, Núm. 4, pp. 1438-1442
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Fault injection emulation for systems in FPGAs: Tools, techniques and methodology, a tutorial
Sensors (Switzerland), Vol. 21, Núm. 4, pp. 1-23
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Low delay non-binary error correction codes based on Orthogonal Latin Squares
Integration, Vol. 76, pp. 55-60
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Reliability Analysis of ASIC Designs with Xilinx SRAM-Based FPGAs
IEEE Access, Vol. 9, pp. 140676-140685
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Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes
IEEE Access, Vol. 9, pp. 138734-138743
2020
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Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction
IEEE Transactions on Device and Materials Reliability, Vol. 20, Núm. 2, pp. 390-394