Publicaciones en las que colabora con LUIS PIÑUEL MORENO (52)

2024

  1. Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

    IEEE Transactions on Circuits and Systems II: Express Briefs

  2. Improving the Representativeness of Simulation Intervals for the Cache Memory System

    IEEE Access, Vol. 12, pp. 5973-5985

2023

  1. Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors

    ACM International Conference Proceeding Series

  2. PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core

    Proceedings of the 20th ACM International Conference on Computing Frontiers 2023, CF 2023

  3. RVfpga: Computer Architecture Course and MOOC Using a RISC-V SoC Targeted to an FPGA and Simulation

    ASEE Annual Conference and Exposition, Conference Proceedings

2022

  1. Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions

    2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

  2. PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability

    IEEE Transactions on Emerging Topics in Computing, Vol. 10, Núm. 3, pp. 1241-1252

2021

  1. RVFPGA: Using a RISC-V core targeted to an FPGA in computer architecture education

    Proceedings - 2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021

2020

  1. Spatio-Temporal Resolution of Irradiance Samples in Machine Learning Approaches for Irradiance Forecasting

    IEEE Access, Vol. 8, pp. 51518-51531

  2. Towards a Malleable Tensorflow Implementation

    Communications in Computer and Information Science

2018

  1. Reuse Detector: Improving the Management of STT-RAM SLLCs

    Computer Journal, Vol. 61, Núm. 6, pp. 856-880

2015

  1. A power measurement environment for PCIe accelerators: Application to the Intel Xeon Phi

    Computer Science - Research and Development, Vol. 30, Núm. 2, pp. 115-124

  2. Balancing task- and data-level parallelism to improve performance and energy consumption of matrix computations on the Intel Xeon Phi

    Computers and Electrical Engineering, Vol. 46, pp. 95-111

  3. Non-negative Matrix Factorization on Low-Power Architectures and Accelerators: A Comparative Study

    Computers and Electrical Engineering, Vol. 46, pp. 139-156

2014

  1. Write-aware replacement policies for PCM-based systems

    Computer Journal, Vol. 58, Núm. 9, pp. 2000-2025

2013

  1. Increasing the Endurance of Phase-Change Memories with Cache Replacement Policies

    Actas de las XXIV Jornadas de Paralelismo

  2. Reducing writes in phase-change memory environments by using efficient cache replacement policies

    Proceedings -Design, Automation and Test in Europe, DATE

2012

  1. Reducing cache hierarchy energy consumption by predicting forwarding and disabling associative sets

    Journal of Circuits, Systems and Computers, Vol. 21, Núm. 7

2011

  1. Hybrid timing-address oriented load-store queue filtering for an x86 architecture

    IET Computers and Digital Techniques, Vol. 5, Núm. 2, pp. 145-157

  2. L1 data cache power reduction using a forwarding predictor

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)