Informática
Facultad
KU Leuven
Lovaina, BélgicaPublicaciones en colaboración con investigadores/as de KU Leuven (57)
2024
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Improving the Representativeness of Simulation Intervals for the Cache Memory System
IEEE Access, Vol. 12, pp. 5973-5985
2023
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Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems
IEEE Transactions on Computers, Vol. 72, Núm. 9, pp. 2548-2560
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COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
Journal of Systems Architecture, Vol. 145
2022
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Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, Núm. 12, pp. 5327-5332
2021
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Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays
IEEE Transactions on Device and Materials Reliability, Vol. 21, Núm. 2, pp. 258-266
2020
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Analysis of functional errors produced by long-Term workload-dependent bti degradation in ultralow power processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Núm. 10, pp. 2122-2133
2019
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A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs
Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019
2018
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Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
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Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
2017
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Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems
Proceedings - IEEE International Symposium on Circuits and Systems
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Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems
2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
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Preface
Proceedings of the 11th European Conference on Games Based Learning, ECGBL 2017
2015
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System level exploration of a STT-MRAM based Level 1 Data-Cache
2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
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System level exploration of a STT-MRAM based level 1 data-cache
Proceedings -Design, Automation and Test in Europe, DATE
2014
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Configuration mapping algorithms to reduce energy and time reconfiguration overheads in reconfigurable systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, Núm. 6, pp. 1248-1261
2013
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Introduction to the thematic issue
Journal of Ambient Intelligence and Smart Environments
2012
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The ABS tool suite: Modelling, executing and analysing distributed adaptable object-oriented systems
International Journal on Software Tools for Technology Transfer, Vol. 14, Núm. 5, pp. 567-588
2010
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Software metadata: Systematic characterization of the memory behaviour of dynamic applications
Journal of Systems and Software, Vol. 83, Núm. 6, pp. 1051-1075
2009
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Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems
Journal of Systems and Software, Vol. 82, Núm. 4, pp. 590-602
2008
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Efficiently scheduling runtime reconfigurations
ACM Transactions on Design Automation of Electronic Systems, Vol. 13, Núm. 4