Publicaciones en las que colabora con JUAN ANTONIO MAESTRO DE LA CUERDA (23)

2023

  1. Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension

    IEEE Transactions on Aerospace and Electronic Systems, Vol. 59, Núm. 5, pp. 5835-5846

  2. RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography

    IEEE Transactions on Computers, Vol. 72, Núm. 3, pp. 682-692

2022

  1. A new radiation-hardened architecture for holographic memory address calculation

    Alexandria Engineering Journal, Vol. 61, Núm. 8, pp. 6181-6190

  2. ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, Núm. 3, pp. 1577-1581

  3. Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors

    Computers and Electrical Engineering, Vol. 99

2021

  1. Fault injection emulation for systems in FPGAs: Tools, techniques and methodology, a tutorial

    Sensors (Switzerland), Vol. 21, Núm. 4, pp. 1-23

  2. Reliability Analysis of ASIC Designs with Xilinx SRAM-Based FPGAs

    IEEE Access, Vol. 9, pp. 140676-140685

2013

  1. An efficient technique to protect serial shift registers against soft errors

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, Núm. 8, pp. 512-516

2012

  1. Implementing concurrent error detection in infinite-impulse-response filters

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 59, Núm. 9, pp. 583-586

2011

  1. A fast and efficient technique to apply Selective TMR through optimization

    Microelectronics Reliability, Vol. 51, Núm. 12, pp. 2388-2401

  2. Validation and optimization of TMR protections for circuits in radiation environments

    Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

2009

  1. A methodology for automatic insertion of selective TMR in digital circuits affected by SEUs

    IEEE Transactions on Nuclear Science

  2. Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study

    Integration, the VLSI Journal, Vol. 42, Núm. 2, pp. 128-136

2008

  1. A new EDAC technique against soft errors based on pulse detectors

    IEEE International Symposium on Industrial Electronics

  2. Automatic insertion of selective TMR for SEU mitigation

    Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

  3. Efficient protection techniques against SEUs for adaptive filters: An echo canceller case study

    IEEE Transactions on Nuclear Science

  4. Fault tolerance analysis of communication system interleavers: The 802.11a case study

    Journal of Signal Processing Systems, Vol. 52, Núm. 3, pp. 231-247

  5. Performance analysis and improvements for a simulation-based fault injection platform

    IEEE International Symposium on Industrial Electronics

2007

  1. A new protection technique for finite impulse response (FIR) filters in the presence of soft errors

    IEEE International Symposium on Industrial Electronics

  2. A simulation platform for the study of soft errors on signal processing circuits through software fault injection

    IEEE International Symposium on Industrial Electronics